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Silicon Labs /EFR32FG23A010F256GM40 /RAC_S /PAENCTRL

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Interpret as PAENCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PARAMP)PARAMP 0 (INVRAMPCLK)INVRAMPCLK 0 (DIV2RAMPCLK)DIV2RAMPCLK 0 (RSTDIV2RAMPCLK)RSTDIV2RAMPCLK

Description

No Description

Fields

PARAMP

PA output level ramping
INVRAMPCLK

Invert PA ramping clock
DIV2RAMPCLK

Div PA ramping clock by 2
RSTDIV2RAMPCLK

Reset Div2 PA ramping clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data